Balanced matrix driver arrangement



Bec. 9, 1969 R, A, @ANGE ET AL 3,483,57

BALANCED MATRIX DRIVER ARRANGEMENT Dec. 9, 1969 R, A, @ANGE ET AL-BALANCED MATRX DRIVER ARRANGEMENT 3 Sheets-Sheet 2 Filed Dec. 22, 1966mwN/ R. A. @ANGE ET AL SASB? Dec. 9, 1969 BALANCED MATRIX DRIVERARRANGEMENT 3 Sheets-Sheet 5 Filed Dec. 22, 1966 rUnited States Patent O3,483,517 BALANCED lvIAIRlX DRlVER ARRANGEMENT Robert A. Gange, BelleMead, and Eugene Nagle, Middletown, NJ., assignors to RCA Corporation, acorporation of Delaware Filed Dec. 22, 1966, Ser. No. 603,307 Int. Cl.H0411 1/56 `U.S. Cl. 340-166 9 Claims This invention relates to a novelmatrix-driver arrangement which is especially useful in providingbalanced outputs to the drive lines of a cryoeleceric memory.

In cryoelectric memories, the sense or output signals are of very smallamplitude. Consequently, great care must be exercised to avoid thegeneration of noise and spurious signals introduced -by way of thedecoder, driver and memory drive lines lest false output signals result.Memory drive lines which are unbalanced with respect to the systemground ar a major source of noise and spurious signals since currentsiiowing in these lines induce voltages in the memory ground plane andsense lines through capacitive coupling. These unwanted signals can beeliminated or at least greatly reduced by employing drive lines whichare structurally balanced, i.e., symmetrical, with respect to the groundplane and by driving these lines from a source which is electricallybalanced with respect to the drive lines.

It is one object of this invention to provide an improved memory andmemory drive arrangement which is both electrically and structurallybalanced.

It is another object of this invention to provide an improved drivesystem which produces balanced output signals from an essentially singleended source.

It is a further object of this invention to provide an improvedmatrix-driver arrangement in which the drivers function also as the laststage of a decoder and in which a stable current is steered through aselected driver in response to an interrogate or control signal.

It is yet another object of this invention to provide a matrix-driverarrangement of the type immediately aforementioned, in which the stablecurrent source and the interrogate signal circuitry are combined in thesame small package as the matrix-drivers to reduce component count andenable compactness, all of which features are compatible with the noiserequirements of a cryoelectric memory system.

In apparatus embodying the invention, each of a first set ofamplifier-driver devices has a like electrode connected in common to oneterminal of a stable source of current, and each one of a second set ofamplierdrivers has one like electrode connected in common to the otherterminal of the stable source. A second electrode of each driver in thefirst set is connected to the second electrode of each driver in thesecond set by way of the primary winding of a separate outputtransformer, and the ends of each transformers secondary winding areelectrically balanced with respect to a reference, e.g. system ground.Any output transformer may be selected by applying enabling signals tothe control electrodes of the two associated amplifier-drivers.

Further, a signal-responsive current shunting or diverting path isconnected across the stable current source and operates in the absenceof a control signal to draw all of the current from the stable source.An applied control signal interrupts the shunting path, whereupon thesource current flows through that one of the transformer primarywindings whose associated amplifier-drivers are receiving enablingsignals.

In the accompanying drawing, like reference characters denote likecomponents; and

FIGURE 1 is a block diagram of a memory and matrix-driver arrangementembodying the invention;

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FIGURE 2 is a simplied diagram of a memory system in which the drivelines are unbalanced;

FIGURE 3 is a simplified diagram of a memory system employing balanceddrive lines; and

FIGURES 4(a) and 4(b) together constitute FIGURE 4, of which FIGURE 4(a)is a schematic diagram of the matrix-drivers, and FIGURE 4(b) is aschematic diagram of a stable current source and a current shuntingpath.

A balanced matrix-driver arrangement and memory system embodying theinvention is illustrated in block form in FIGURE l. This arrangement isespecially useful in providing balanced output signals to a cryoelectricmemory 10 of the type which employs drive lines operated in pairs, whichdrive means are structurally balanced with respect to the memory groundplane or planes. A suitable example of such a memory is illustrated anddescribed in the copending application of Robert A. Gange, Ser. No.584,433, iiled Oct. 5, 1966 for Cryoelectric Memories, which byreference thereto is made a part hereof.

As explained in that copending application, so-called a, b cryoelectricmemory systems prior to the ones described in the copending applicationemployed single conductors as the memory drive lines. Such a prior artsystem is illustrated in rudimentary form in FIGURE 2 of the presentapplication. Such a system generally comprises one or more ground planes14, only one of which is illustrated, each of which has a large numberof cryoelectric memory or storage elements thereon. Each of thesestorage elements, for example the storage element represented by shadedarea 16, is linked by two drive lines, one line from a unit 18 labelledvb SELECT, and one line from a unit 20 labelled a SELECT. Theseselection units may include decoders and drivers, as is well-known inthe art. For purposes of convenience, only the drive lines 22b and `24awhich link the element 16 are illustrated in FIGURE 2. It will be notedthat each of these lines is grounded at its far end, whereby the linesare unbalanced with respect to the ground plane 14.

The selection units 18 and 20 and the system ground usually are locatedoutside the low temperature bath, e.g. cryostat, while the `groundplanes 14 and the portions of the drive lines linking same are locatedwithin the cryostat. The line 26 which connects the ground plane 14 tosystem ground may be several feet in length, whereby this line 26appears as an inductor to any signals i11- duced in the ground plane 14.

There is capacitive coupling between each of the drive lines, e.g. lines22b and 24a, and the ground plane 14, and by way of the ground plane tothe sense line or lines (not illustrated). These distributedcapacitances are illustrated for convenience as lumped capacitors 28,30. Each time a positive going signal is applied to the drive line 22h,lwhether the signal be a drive current, noise, etc., capacitor 28charges in the polarity direction indicated. Since one end of this line22h is grounded and the positive signal is applied at the other end, avoltage gradient is present along the line, and all of the distributedcapacitances charge in the same polarity direction. The same is true forany positive going signal on the other line 24a. These charge currentsmust llow to system ground by way of the lead 26, and the inductancethereof results in a voltage being induced on the ground plane 14. Themovement of voltage of the ground plane occurs with greater severity inthe absence o-f connection 26. Also, a voltage is induced on the senseline due to this capacitance, and the induced signal may be of muchgreater amplitude than the small amplitude sense signals which areinduced on the sense line during a read operation.

As described in the copending application, the aforementioned inducedsignals are avoided in a memory system of the type illustrated thereinwhich employs two conductors for each drive line. The manner in whichthis is accomplished is illustrated in simple form in FIGURE 3. Theimproved system is one in which the drive lines are structurally andelectrically balanced with respect to the ground plane 14. One of thetwo conductors of the drive line may be thought of as an outgoingconductor and the other a return conductor. For example, the single bdrive line shown in full includes an outgoing conductor 22b and a returnconductor 22b. The voltages applied at the ends of this line bytheselection unit are balanced with respect to system ground. That is tosay, when it is desired to energize this line, the free end of conductor22b has a voltage +V applied thereto and the free end of conductor 22bhas a voltage -V of equal and opposite polarity applied thereto. Thecenter point 32 of the line then is a virtual ground. Since the line isstructurally balanced with respect to the ground plane 14, equalportions of the conductors 22b and 22b overlie the ground plane 14, andsince the voltages on the two different conductors 22b and 22b' are ofequal and opposite polarity, the capacitors 28 and 28 conduct chargecurrent in opposite directions with respect to the ground plane 14. As aresult, the net current flowing in the ground plane 14 due to the signalon this pair of conductors is Zero, since the two charge currents cancelone another. As a consequence, no current flows in the ground lead 26,there is no voltage induced on the ground plane 14 and no spurioussignal coupled to or induced in the sense line. The above descriptionassumes that the conductors 22b and 22bl (and all other pairs of drivelines) are structurally and electrically balanced with respect to systemground, and assumes further a balanced drive source for the lines. It isthe purpose of the Present invention to provide Stich a balanced driverarrangement, which may be used as the b SELECT unit 18 or the a SELECTunit 20.

With reference again to FIGURE l, the arrangement embodying theinvention comprises a stable current source which has connected acrossthe terminals thereof a current diverting or shunting path which maycomprise a rst signal controlled switch 42 in series with a secondsignal controlled switch 44. The junction of these two switches may beconnected to system ground. A switch control 46 receives interrogate orcontrol signals from a source 48 and, in response thereto, opens orcloses the switches concurrently. In the absence of a control signal,both of the switches are closed to provide a low impedance shunt pathwhich draws all of the current supplied by the source 40. In response toa control signal, switch control 46 operates to open the switches 42 and44, whereby the current from source 40 may flow through drivers (to bedescribed) to produce signals on a selected memory drive line.

The arrangement further includes two sets of decoderdrivers 52, 54 inwhich the drivers function also as matrix switches. Each of the decoders52, 54, receives binary input signals, as from a memory address register56, 58. Although these registers are separately illustrated in thedrawing, it should be understood that, in actual practice, each of thedecoders may receive different inputs from a single memory addressregister or other addressing means. The uppermost output of thedecoder-driver unit 52 is connected to the uppermost output 62 of theother decoder-driver unit 54 by way of the parallel combination of atransformer primary winding 64 and an adjustable resistor 66. Thesecondary winding 68 of this transformer has its opposite ends connectedto different ones of a pair of conductors of a memory drive line, forexample the conductors 22b, 22b (or 24a, 24a) of FIGURE 3. Connectedacross the secondary winding 68 is a potentiometer 70 which has amovable arm '72 connected to system ground, which arm 72 may bepositioned so that the voltages applied to the conductors 22b and 22bare equal in amplitude and opposite in polarity with respect to systemground.

In like manner, the uppermost output 60 of the driver 52 is connectedthrough separate transformer primary windings and paralleling resistorsto each of the other outputs of the decoder-driver 54. Only one of thelatter connections is shown in full for convenience of drawing; however,it will be understood that similar connections appear between points a fand a f', respectively. Similarly, each of the other outputs of thedecoderdriver 52 is connected to each of the outputs of thedecoder-driver 54 by way of separate transformer primary windings andparallel resistors, whereby the drivers function also as matrixswitches. These connections may be understood rnore fully by referringto FIGURE 4.

FIGURE 4 is made up of FIGURES 4(a) and 4to) which are, respectively,schematic drawings of the matrixdrivers 52, 54 and the current source 40with its associated switches 42, 44. Refer now to FIGURE 4( bi. Thecurrent source 40 is illustrated at the top of this drawing ascomprising a PNP transistor having its base returned to a suitable biaspotential, such as 6 volts, and having its emitter connected by way of avariable resistor 82 to the emitter of an NPN transistor 84. This lattertransistor has its base connected to +6 volts, for example, the two basevoltages being of the proper magnitude and polarity to bias thetransistors 80 and 84 in a conducting condition. The collector oftransistor S4 is connected by way of an inductor 86, which may be a wirethrough a ferrite bead, to the positive terminal ot' a battery 88.Similarly, the collector of the other transistor 80 is connected by wayof an inductor 90 to the negative terminal of a battery 92. Inductors 86and 90 help to prevent any oscillations during switching. The values ofthe batteries and other components in the circuit just described areselected to provide a stable source of current.

The iirst switch 42 is illustrated as an NPN transistor having itsemitter grounded and having its collector connected to the positiveterminal of battery 92. The other switch 44 is illustrated as a PNPtransistor 102 having its emitter grounded and having its collectorconnected to the negative terminal of battery 88. Transistor 100 has itsbase returned by way of a base biasing resistor 104 to a bias point of-12 volts. Additionally, the base is connected through a series of levelshifting diodes 106 to a junction point 108, which junction point isconnected by the series combination of a level shift diode 110 and aresistor 112 to a source of +12 volts. A further diode 114 is connectedbetween the collector of transistor 100 and an intermediate point on thediode chain 106.

The base of the other transistor 102 is returned by way of a biasingresistor to +12 volts, and is connected via a pair of series connectedlevel shifting diodes 124 to a junction point 122. A resistor 126 and apair of level shift diodes 128 are serially connected between junction122 and a source of l2 volts. A further diode 130 is connected betweenthe collector of transistor 102 and junction point 122.

The switch control 46 (FIGURE 1) is schematically illustrated in FIGURE4( b) as comprising an NPN transistor 134 having its collector connectedto the junction 108 and its emitter connected to the junction 122. Thebase lof this transistor is returned by way of a base bias resistor 136to the -12 Volt supply. Several similarly poled level shifting diodes148 are serially connected between the base of transistor 134 and ajunction point 138. A diode 140 and a resistor 142 are connected betweenjunction point 138 and the +12 volt supply. Another diode 144 and aresistor 146 are serially connected between junction point 138 andsystem ground, with the point between resistor 146 and the cathode ofdiode 144 connected to the source 48 of interrogate or control pulses.

Suitable circuitry for the matrix-drivers 52 and 54 are illustrated atthe left and right sides7 respectively, of FIGURE 4(a). Driver unit 52comprises a plurality of PNP transistors, four transistors 16011, 160b,1601: and 16011 being shown for convenience. The emitters of thesetransistors are connected in common and to the positive terminal of thebattery 92 (FIGURE 4(b)). The collector circuit of each of thesetransistors includes a similar clamping arrangement, and the clampingarrangement for transistor 16011 will be described as illustrative ofall others. Transistor 16011 has its collector electrode connected to ajunction 16411 by way of an inductor 16211, which may be a wire througha ferrite bead. A potentiometer 16611 is connected between circuitground and a source of +6 volts. Sliding arm 16811 of the potentiometeris coupled to the junction 16411 by the series combination of a resistor17011 and a diode 17211. A capacitor 17411 is connected between circuitground and the junction of resistor 17011 and the anode of diode 17211.When transistor 16011 is in a nonconducting condition, this clampingarrangement provides a voltage at the juction point 16411 which hasabout the same value as the voltage thereat when the transistor isconducting, thereby helping to prevent noise. The wire through ferritebead 16211 helps to prevent any oscillations on the output linesconnected to the junction 16411.

The other set of drivers, located at the right-hand side of FIGURE4(11), comprises a plurality of NPN transistors, four transistors 1801118011 being shown. In general, the number of transistors in this set isthe same as the number of transistors in the lirst set. Each of thetransistors 18011 18011 has its emitter connected to the negativeterminal of battery 8S (FIGURE 4(6)). A diode 18211 182d is connectedacross the emitter-base junction of each of the transistors 18011 18011,respectively, and is poled to conduct forward current in the samedirection, relative to the base electrode, as the emitter-base junctionof the transistor. Each transistor has a similar collector circuit. Byway of example, transistor 18011 has its collector connected by way ofan inductor 18411, such as a wire through a ferrite bead, to a junctionpoint 18611. This inductor helps to prevent oscillations in the outputlines connected at junction point 18611. A resistor 18811 is conectedbetween that junction point and circuit ground.

Each of the transistors 16011 16011' in the first set has its collectorconnected to the collector of each and every transistor in the secondset by way of a similar network. Only the network 19011 connecting thecollectors of transistor 16011 and transistor 18011 is shown in detailfor convenience of drawing. The other networks, which are similar, arerepresented in the drawing by rectangular boxes 19011 19011. In theillustrative example, wherein there are four transistors in each of thedriver sets, there is a total of sixteen networks connected between thecolectors of the various transistors. In the more general case, whereinthere are N transistors in each set, there is a total of N2intercoupling networks, and thus N2 outputs from the arrangement. Thus,the transistors 16011 16011 and 18011 18011, in addition to functioningas drivers, also operate as matrix switches. In this manner, a largenumber of outputs is available for a very small number of transistors.

The network 19011 connected between the junction point 16411 in thecollector circuit of transistor 16011 and the junction point 18611 inthe collector circuit of transistor 18011 comprises the parallelcombination of a variable resistor 66 `and the primary winding 64 of anoutput transformer. Resistor 66 is provided for trimming the linecurrent. The right hand end of the parallel combination is connecteddirectly to junction point 186a; the left hand end is coupled tojunction point 16411 via a diode 19411.

The secondary winding 68 of this transformer has its opposite endsconnected to the two dilerent conductors of a drive line in thecryoelectric memory. By way of example, these two conductors may be theconductors 2211 and 2211 illustrated in FIGURE 3. A potentiometer 70 isconnected across the secondary winding and has its adjustable arm 72connected to system ground, whereby the adjustable arm 72 may bepositioned so that the Voltages at the opposite ends of the secondarywinding 68 are of equal amplitude and opposite Ipolarity relative tosystem ground. An electrostatic shield 74 reduces electrostatic couplingbetween the primary and secondary windings of the transformer.Electrostatic coupling is further reduced by minimizing voltage swingsacross the primary of the transformer. This latter feature is realizedby the collector clamping arrangement previously described.

Consider now the operation of the FIGURE 4 arrangement. Ordinarily thebase electrodes of all but one of the transistors 16011 16011 in thelirst set are maintained at +6 volts, and the base electrodes of allexcept one of the transistors 18011 11 in the second set are maintainedat 6 volts. These voltages, for example, may be provided Aby the outputsof decoders. Any given one of the output networks a 19011 may beselected by applying input voltages of +2 volts and 2 volts at the basesof the transistors in the first and second sets which are associatedwith that output network. By way of example, output network 190a isselected by applying +2 volts at the base of transistor 16011 and -2volts at the base of transistor 18011; input network 190d is selected byapplying +2 volts at the base of transistor 16011 and 2 volts at thebase of transistor 18011', etc.

Ordinarily, the control signal source 48 (FIGURE 4(17) supplies an inputof ground potential at the cathode of diode 144. Diode 144 conductscurrent from the +12 volt supply via resistor 142 and diode 140.Assuming silicon diodes, the voltage at junction 138 may be about +0.7volt for this condition. Due to the level shift diodes 148, the voltageat the base of control transistor 134 is approximately 4 volts. For thiscondition, transistor 134 is maintained in a nonconducting condition bythe voltage applied at its emitter electrode from the biasingarrangement in the base input circuit of transistor 102. Transistor 102is biased into conduction, and its base electrode is about 0.7 volt. Thevoltage at junction 122 is approximately 2.1 volts, Iwhich voltage ismore positive than the voltage at the base of transsistor 134. Diode130, connected between the collector of transistor 102 and junctionpoint 122, prevents transistor 102 from becoming saturated, therebypreventing minority carrier storage in this transistor, and enablingthis transistor to be turned off with minimum delay. A further functionof this diode 130 is that it essentially clamps the voltage at thecollector of transistor 102 at approximately 1.4 volts rather than atground potential when transistor 102 is conducting. The importance ofthis feature will be discussed hereinafter.

With control transistor 134 biased in a nonconducting condition,transistor 100 is rendered conductive. The feedback diode 114 preventssaturation of the transistor 100. Additionally, this diode clamps thecollector voltage at yapproximately +l.4 volts, whereas the voltage atthe collector would fall close to ground potential if the transistor 100were allowed to saturate.

With +1.4 volts at the collector of transistor 100 and 1.4 volts at thecollector of transistor 102, the emitterbase junctions of all of thetransistors 16011 16011 and 18011 18011 (FIGURE 4 (b)) are reversebiased. All of the current from the stable current source 40 then owsthrough the transistors 100 and 102.

Let it be assumed that transistor 16011 has a base input voltage of +2Volts and transistor 18011 has a base input voltage of 2 volts. All ofthe other transistors 160b 16011 have base inputs of +6 volts and all ofthe other transistors 18011 18011 have base inputs of 6 volts. When aninterrogate or control pulse from source 48 is applied at the base inputterminal of control transistor 134, diode 144 becomes reverse biased.The voltage at the base of transistor 134 at this instant in time is afunction of the values of resistors 136 and 142. Resistor 136 is chosento be much much greater than the value of transistor 142, whereby thevoltage at the base of transistor 134 rises in a positive direction andturns on the transistor 134.

The more positive voltage which appears at the emitter of transistor 134when transistor 134 conducts biases otf transistor 102. Further, thevoltage at the collector of transistor 134 becomes less positive whentransistor 134 conducts, the transistor 100 becomes biased in anonconducting condition. The current hunting path through transistors100 and 102 then is interrupted, and the current from stable source 40becomes available to the selected drivers (transistors 160:1 andtransistor 180:1). The voltage at the emitter of transistor 160a rises-from -l-l.4 volts to approximately +2.7 volts, and the voltage at theemitter of transistor 180:1 falls from -l.4 volts to 2.7 volts, or atotal voltage change of approximately 2.6 volts across the terminals ofthe current source 40. In the absence of the feedback diodes 114 and 130(FIGURE 4 (110) this change in voltage would be approximately 5.4 volts.Thus, the feedback diodes 114 and 130 limit the voltage swing across thecurrent source to a small value during switching. This has the effect ofrequiring less current from the source to charge any capacitance on thecommon lines from the collector of transistor 100 to the emitters of thedecoders 160a 160d and the line from the collector of transistor 102 tothe emitters of transistor 180a 180o'. More current then is availableinitially to the decoders than would otherwise be the case, therebyallowing for a fast rise time of the output signal. Moreover, this smallchange in voltage results in a stiffer current source.

Current from the stable source 40 flows, in the conventional sense, fromthe positive terminal of battery 92, through the emitter-collector pathof transistor 160Q, diode 194a, resistor 66 and primary winding 64, andthence through the collector-emitter path of transistor 180a to thenegative terminal of battery 88. This change in current through primarywinding 64 induces a voltage across secondary winding, 68, the voltagesat the opposite ends of the latter being of equal ampiltude and ofopposite polarity relative to system ground Transistor 160e saturates;however, its collector voltage changes very little, if any, due to theaction of the collector clamping arrangement.

Transistor 180a is prevented from saturating by the external diode 182aacross its emitter-base junction. Although the voltage changes atcollector junction 186a, there is practically no change in currentthrough the nonselected output networks connected thereto because of thelarge values of resistance in the collector clamping arrangements ofnonconducting transistors 160b 160d. The various diodes 194b 19411prevent sneak current path through nonselected output networks 190b19011.

In a similar manner, any other output network 190b 19011 can beenergized selectively by applying enabling signals at the bases of thetransistors associated therewith. Of course, only one output network isselected at any one time.

In addition to various inductors, etc., described previously, forpreventing oscillations and noise, it has been found that even greaterstability is achieved by connecting a resistor 200 and a capacitor 202in series across the terminals of the current source 40 (FIGURE 4(b)) todamp any oscillations that might occur. The value of resistor 200 isselected to be about equal to the net resistive impedance R betweenthese terminals, and the value C of capacitor 202 is chosen so that, inrelation to the value L of net inductance across those terminals, R2=L/C.

What has been illustrated and described is an arrangement for providingbalanced output signals from a singleended source, in which the driversfunction also as matrix switches, and in which the number of outputs canbe easily increased at the expense of a much smaller increase in thenumber of drivers, whereby component count is held to a low number.Further, the single current source and steering control therefore may becombined :n the same small package as the driver circuitry to enablecompactness. All of these features are compatible with the noiserequirements of a balanced cryoelectric memory system.

What is claimed is:

1. The combination comprising:

a stable current source having an input terminal and an output terminal;

first and second groups of junction points;

a first set of signal responsive switch means each having a currentcarrying path connected between said output terminal and a dilierent oneof the junction points in the first group;

a second set of signal responsive switch means each having a currentcarrying path connected between said input terminal and a different oneof the junction points in the second set;

a plurality of output transformers each having a primary winding and asecondary winding, each of the plurality of the primary windings beingconnected in circuit between a different combination of two junctionpoints, one of which is in the rst group and the other of which is inthe second group;

means connected across the two ends of each secondary winding forbalancing the voltages at the two ends with respect to a referencepotential;

input means applying enabling signals to any selected one of the switchmeans in the rst set and any selected one of the switch means in thesecond set concurrently; and

a signal responsive current diverting path, exclusive of the switchmeans, connected across the input and output terminals of the stablesource and having control means for rendering said path blocked orunblocked selectively, said path in the unblocked condition receivingthe current from said stable source.

2. The combination as claimed in claim 1, wherein the switch means inthe first and second sets are amplifying devices.

3. The combination as claimed in claim 1, wherein the switch means inthe first set are transistors of one conductivity type each having onelike electrode connected to the output terminal of the stable source,and wherein the switch means in the second set are transistors of theopposite conductivity type each having one like electrode connected tothe input terminal of the stable source.

4. The combination as claimed in claim 1, wherein the balancing meansconnected across the ends of a secondary winding is a potentiometerhaving a movable tap maintained at said reference potential.

S. The combination as claimed in claim 4, wherein there are N switchmeans in the lirst set, N switch means in the second set, and N sets ofN output transformers each, wherein all of the primary windings of a sethave one end connected to the same junction point in the first group,and wherein each of the primary windings in any given group has itsother end connected to a different one of the junction points in thesecond group.

6. The combination as claimed in claim 4, including a cryoelectricmemory having at least one ground plane, drive lines linking said groundplane and being structurally balanced with respect thereto, and meansconnecting each secondary winding across the ends of a different one ofsaid drive lines.

7. The combination as claimed in claim 6, wherein the switch means inthe rst set are transistors of one conductivity type, and wherein theswitch means in the second set are transistors of the oppositeconductivity type.

8. The combination as claimed in claim 6, wherein each of saidtransformers has an electrostatic shield between its primary andsecondary windings.

9. The combination as claimed in claim 4, including References Citedseparate clamping means connected at each of the junction points of oneof the groups of junction points, each UNITED STATES PATENTS clampingmeans providing, in the inoperative state of the 3,235,840 2/1966 Sturm3,4() 165 associated switch means, a voilage at its associated junc- 53,336,581 g/1967 Jorgensen et a1. 340 166 XR tion point which has thesame value as the voltage thereat when the associated switch means isoperative. DONALD J. YUSKO, Primary Examiner

1. THE COMBINATION COMPRISING: A STABLE CURRENT SOURCE HAVING AN INPUTTERMINAL AND AN OUTPUT TERMINAL; FIRST AND SECOND GROUPS OF JUNCTIONPOINTS; A FIRST SET OF SIGNAL RESPONSIVE SWITCH MEANS EACH HAVING ACURRENT CARRYING PATH CONNECTED BETWEEN SAID OUTPUT TERMINAL AND ADIFFERENT ONE OF THE JUNCTION POINTS IN THE FIRST GROUP; A SECOND SET OFSIGNAL RESPONSIVE SWITCH MEANS EACH HAVING A CURRENT CARRYING PATHCONNECTED BETWEEN SAID INPUT TERMINAL AND A DIFFERENT ONE OF THEJUNCTION POINTS IN THE SECOND SET; A PLURALITY OF OUTPUT TRANSFORMERSEACH HAVING A PRIMARY WINDING AND A SECONDARY WINDING, EACH OF THEPLURALITY OF THE PRIMARY WINDINGS BEING CONNECTED IN CIRCUIT BETWEEN ADIFFERENT COMBINATION OF TWO JUNCTION POINTS, ONE OF WHICH IS IN THEFIRST GROUP AND THE OTHER OF WHICH IS IN THE SECOND GROUP; MEANSCONNECTED ACROSS THE TWO ENDS OF EACH SECONDARY WINDING FOR BALANCINGTHE VOLTAGES AT THE TWO ENDS WITH RESPECT TO A REFERENCE POTENTIAL;INPUT MEANS APPLYING ENABLING SIGNALS TO ANY SELECTED ONE OF THE SWITCHMEANS IN THE FIRST SET AND ANY SELECTED ONE OF THE SWITCH MEANS IN THESECOND SET CONCURRENTLY; AND A SIGNAL RESPONSIVE CURRENT DIVERTING PATH,EXCLUSIVE OF THE SWITCH MEANS, CONNECTED ACROSS THE INPUT AND OUTPUTTERMINALS OF THE STABLE SOURCE AND HAVING CONTROL MEANS FOR RENDERINGSAID PATH BLOCKED OR UNBLOCKED SELECTIVELY, SAID PATH IN THE UNBLOCKEDCONDITION RECEIVING THE CURRENT FROM SAID STABLE SOURCE.